EP2S60F1020C3

SKU: 82344

Manufacturer: Intel

FPGA Stratix® II Family 60440 Cells 816.99MHz 90nm Technology 1.2V 1020-Pin FC-FBGA

30 parts IN STOCK

Shipped from :

Netherlands

Expected Ships :

Rohs State : Need to verify

Increments of 0 pcs

Products specifications

EU RoHS	Not Compliant
ECCN (US)	3A001.a.7.a
Part Status	Obsolete
HTS	8542.39.00.01
SVHC	Yes
SVHC Exceeds Threshold	Yes
Automotive	No
PPAP	No
Family Name	Stratix® II
Process Technology	90nm
User I/Os	718
Number of I/O Banks	8
Operating Supply Voltage (V)	1.2
Shift Registers	Utilize Memory
Logic Elements	60440
Number of Multipliers	144 (18x18)
Program Memory Type	SRAM
Embedded Memory (Kbit)	2484.6
Total Number of Block RAM	2+255+329
IP Core	RapidIO to AXI Bridge Controller (RAB)
Provider Name	Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA
Device Logic Units	60440
Number of Global Clocks	16
Device Number of DLLs/PLLs	12
Dedicated DSP	36
Programmability	No
Reprogrammability Support	No
Copy Protection	No
Opr. Frequency (MHz)	816.99
In-System Programmability	Yes
Speed Grade	3
GMACs	37.8
Mega Multiply Accumulates per second	37800
Differential I/O Standards	LVPECL
Single-Ended I/O Standards	HSTL
Maximum I/O Performance	1Gbps
External Memory Interface	DDR2 SDRAM
Operating Supply Voltage-Min (V)	1.15
Operating Supply Voltage-Max (V)	1.25
I/O Voltage (V)	1.5
Operating Temperature-Min	0
Operating Temperature-Max	85
Supplier Temperature Grade	Commercial
Tradename	Stratix
Original Package	FC-FBGA
Pin Count	1020
Standard Package Method	BGA
Terminal Form	Surface Mount
Package Height	3(Max)
Package Length	33
Package Width	33
PCB changed	1020

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Products specifications

EU RoHS	Not Compliant
ECCN (US)	3A001.a.7.a
Part Status	Obsolete
HTS	8542.39.00.01
SVHC	Yes
SVHC Exceeds Threshold	Yes
Automotive	No
PPAP	No
Family Name	Stratix® II
Process Technology	90nm
User I/Os	718
Number of I/O Banks	8
Operating Supply Voltage (V)	1.2
Shift Registers	Utilize Memory
Logic Elements	60440
Number of Multipliers	144 (18x18)
Program Memory Type	SRAM
Embedded Memory (Kbit)	2484.6
Total Number of Block RAM	2+255+329
IP Core	RapidIO to AXI Bridge Controller (RAB)
Provider Name	Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA
Device Logic Units	60440
Number of Global Clocks	16
Device Number of DLLs/PLLs	12
Dedicated DSP	36
Programmability	No
Reprogrammability Support	No
Copy Protection	No
Opr. Frequency (MHz)	816.99
In-System Programmability	Yes
Speed Grade	3
GMACs	37.8
Mega Multiply Accumulates per second	37800
Differential I/O Standards	LVPECL
Single-Ended I/O Standards	HSTL
Maximum I/O Performance	1Gbps
External Memory Interface	DDR2 SDRAM
Operating Supply Voltage-Min (V)	1.15
Operating Supply Voltage-Max (V)	1.25
I/O Voltage (V)	1.5
Operating Temperature-Min	0
Operating Temperature-Max	85
Supplier Temperature Grade	Commercial
Tradename	Stratix
Original Package	FC-FBGA
Pin Count	1020
Standard Package Method	BGA
Terminal Form	Surface Mount
Package Height	3(Max)
Package Length	33
Package Width	33
PCB changed	1020