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    S29WS512P0PBFW000

    SKU: 122868
    NOR Flash Parallel/Serial 1.8V 512M-bit 32M x 16 80ns 84-Pin VTFBGA Tray
    980 parts IN STOCK
    Shipped from :
    Netherlands
    Expected Ships :
    Rohs State : Need to verify

    QUANTITY

    Increments of 0 pcs
    Products specifications
    EU RoHS Compliant
    ECCN (US) 3A991.b.1.a
    Part Status Obsolete
    HTS 8542.32.00.51
    Automotive No
    PPAP No
    Cell Type NOR
    Chip Density (bit) 512M
    Architecture Sectored
    Boot Block Yes
    Block Organization Asymmetrical
    Location of Boot Block Bottom
    Address Bus Width (bit) 25
    Sector Size 32Kbyte x 8
    Bank Size 32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32Mb
    Number of Banks 16
    Page Size 8Words
    Number of Bits/Word (bit) 16
    Number of Words 32M
    Programmability Yes
    Timing Type Asynchronous
    Max. Access Time (ns) 80
    Maximum Erase Time (s) 616/Chip
    Maximum Page Access Time (ns) 20
    Maximum Programming Time (ms) 1008000/Chip
    OE Access Time (ns) 13.5
    Process Technology 90nm
    Interface Type Parallel
    Operating Supply Voltage-Min (V) 1.7
    Maximum Operating Frequency (MHz) 66
    Typical Operating Supply Voltage (V) 1.8
    Operating Supply Voltage-Max (V) 1.95
    Programming Voltage (V) 1.7 to 1.95
    Operating Current (mA) 80
    Page Read Current (mA) 15
    Program Current (mA) 60
    Operating Temperature-Min -25
    Operating Temperature-Max 85
    Supplier Temperature Grade Wireless
    Command Compatible Yes
    ECC Support No
    Support of Page Mode Yes
    Minimum Endurance (Cycles) 100000(Typ)
    Packing Method Tray
    Original Package VTFBGA
    Pin Count 84
    Standard Package Method BGA
    Terminal Form Surface Mount
    Package Height 0.76(Max)
    Package Length 11.6
    Package Width 8
    PCB changed 84
    Products specifications
    EU RoHS Compliant
    ECCN (US) 3A991.b.1.a
    Part Status Obsolete
    HTS 8542.32.00.51
    Automotive No
    PPAP No
    Cell Type NOR
    Chip Density (bit) 512M
    Architecture Sectored
    Boot Block Yes
    Block Organization Asymmetrical
    Location of Boot Block Bottom
    Address Bus Width (bit) 25
    Sector Size 32Kbyte x 8
    Bank Size 32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32Mb
    Number of Banks 16
    Page Size 8Words
    Number of Bits/Word (bit) 16
    Number of Words 32M
    Programmability Yes
    Timing Type Asynchronous
    Max. Access Time (ns) 80
    Maximum Erase Time (s) 616/Chip
    Maximum Page Access Time (ns) 20
    Maximum Programming Time (ms) 1008000/Chip
    OE Access Time (ns) 13.5
    Process Technology 90nm
    Interface Type Parallel
    Operating Supply Voltage-Min (V) 1.7
    Maximum Operating Frequency (MHz) 66
    Typical Operating Supply Voltage (V) 1.8
    Operating Supply Voltage-Max (V) 1.95
    Programming Voltage (V) 1.7 to 1.95
    Operating Current (mA) 80
    Page Read Current (mA) 15
    Program Current (mA) 60
    Operating Temperature-Min -25
    Operating Temperature-Max 85
    Supplier Temperature Grade Wireless
    Command Compatible Yes
    ECC Support No
    Support of Page Mode Yes
    Minimum Endurance (Cycles) 100000(Typ)
    Packing Method Tray
    Original Package VTFBGA
    Pin Count 84
    Standard Package Method BGA
    Terminal Form Surface Mount
    Package Height 0.76(Max)
    Package Length 11.6
    Package Width 8
    PCB changed 84