SIR182DP-T1-RE3

SKU: 127484

Manufacturer: Vishay

Trans MOSFET N-CH 60V 117A 8-Pin PowerPAK SO EP T/R

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Netherlands

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Products specifications

EU RoHS	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8541.29.00.95
Automotive	No
PPAP	No
Product Category	Power MOSFET
Configuration	Single Quad Drain Triple Source
Process Technology	TrenchFET
Channel Mode	Enhancement
Channel Type	N
Number of Elements per pcs	1
Maximum Drain Source Voltage (V)	60
Maximum Gate Source Voltage (V)	±20
Maximum Gate Threshold Voltage (V)	3.6
Maximum Continuous Drain Current (A)	117
Maximum Gate Source Leakage Current (nA)	100
Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	2.8@10V
Typical Gate Charge @ Vgs (nC)	42.2@10V
Typical Gate Charge @ 10V (nC)	42.2
Typical Gate to Drain Charge (nC)	6.7
Typical Gate to Source Charge (nC)	12.2
Typical Reverse Recovery Charge (nC)	71
Typical Input Capacitance @ Vds (pF)	3250@30V
Typical Reverse Transfer Capacitance @ Vds (pF)	50@30V
Minimum Gate Threshold Voltage (V)	2
Typical Output Capacitance (pF)	840
Maximum Power Dissipation (mW)	5000
Typical Fall Time (ns)	10
Typical Rise Time (ns)	23
Typical Turn-Off Delay Time (ns)	21
Typical Turn-On Delay Time (ns)	15
Operating Temperature-Min	-55
Operating Temperature-Max	150
Packing Method	Tape and Reel
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)	25
Typical Diode Forward Voltage (V)	0.75
Typical Gate Plateau Voltage (V)	3.9
Typical Reverse Recovery Time (ns)	59
Maximum Diode Forward Voltage (V)	1.1
Minimum Gate Resistance (Ohm)	0.2
Maximum Gate Resistance (Ohm)	1.3
Maximum Positive Gate Source Voltage (V)	20
Original Package	PowerPAK SO EP
Pin Count	8
Standard Package Method	SOP
Terminal Form	Surface Mount
Package Height	1.07(Max)
Package Length	4.9
Package Width	5.89
PCB changed	8

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Products specifications

EU RoHS	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8541.29.00.95
Automotive	No
PPAP	No
Product Category	Power MOSFET
Configuration	Single Quad Drain Triple Source
Process Technology	TrenchFET
Channel Mode	Enhancement
Channel Type	N
Number of Elements per pcs	1
Maximum Drain Source Voltage (V)	60
Maximum Gate Source Voltage (V)	±20
Maximum Gate Threshold Voltage (V)	3.6
Maximum Continuous Drain Current (A)	117
Maximum Gate Source Leakage Current (nA)	100
Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	2.8@10V
Typical Gate Charge @ Vgs (nC)	42.2@10V
Typical Gate Charge @ 10V (nC)	42.2
Typical Gate to Drain Charge (nC)	6.7
Typical Gate to Source Charge (nC)	12.2
Typical Reverse Recovery Charge (nC)	71
Typical Input Capacitance @ Vds (pF)	3250@30V
Typical Reverse Transfer Capacitance @ Vds (pF)	50@30V
Minimum Gate Threshold Voltage (V)	2
Typical Output Capacitance (pF)	840
Maximum Power Dissipation (mW)	5000
Typical Fall Time (ns)	10
Typical Rise Time (ns)	23
Typical Turn-Off Delay Time (ns)	21
Typical Turn-On Delay Time (ns)	15
Operating Temperature-Min	-55
Operating Temperature-Max	150
Packing Method	Tape and Reel
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)	25
Typical Diode Forward Voltage (V)	0.75
Typical Gate Plateau Voltage (V)	3.9
Typical Reverse Recovery Time (ns)	59
Maximum Diode Forward Voltage (V)	1.1
Minimum Gate Resistance (Ohm)	0.2
Maximum Gate Resistance (Ohm)	1.3
Maximum Positive Gate Source Voltage (V)	20
Original Package	PowerPAK SO EP
Pin Count	8
Standard Package Method	SOP
Terminal Form	Surface Mount
Package Height	1.07(Max)
Package Length	4.9
Package Width	5.89
PCB changed	8