SI4511DY-T1-E3

SKU: 148783

Manufacturer: Vishay

Trans MOSFET N/P-CH 20V 7.2A/4.6A 8-Pin SOIC N T/R

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Netherlands

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Products specifications

EU RoHS	Compliant
ECCN (US)	EAR99
Part Status	Obsolete
HTS	8541.29.00.95
Automotive	No
PPAP	No
Product Category	Power MOSFET
Configuration	Dual Dual Drain
Process Technology	TrenchFET
Channel Mode	Enhancement
Channel Type	N
Number of Elements per pcs	2
Maximum Drain Source Voltage (V)	20
Maximum Gate Source Voltage (V)	±16@N Channel
Maximum Gate Threshold Voltage (V)	1.8@N Channel
Operating Junction Temperature (°C)	-55 to 150
Maximum Continuous Drain Current (A)	7.2@N Channel
Maximum Gate Source Leakage Current (nA)	100
Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	14.5@10V@N Channel
Typical Gate Charge @ Vgs (nC)	11.5@4.5V@N Channel
Typical Gate to Drain Charge (nC)	3.3@N Channel
Typical Gate to Source Charge (nC)	4.1@P Channel
Minimum Gate Threshold Voltage (V)	0.6
Typical Output Capacitance (pF)	399@N Channel
Maximum Power Dissipation (mW)	2000
Typical Fall Time (ns)	15@N Channel
Typical Rise Time (ns)	12@N Channel
Typical Turn-Off Delay Time (ns)	55@N Channel
Typical Turn-On Delay Time (ns)	25@P Channel
Operating Temperature-Min	-55
Operating Temperature-Max	150
Packing Method	Tape and Reel
Maximum Positive Gate Source Voltage (V)	12
Maximum Continuous Drain Current on PCB @ TC=25°C (A)	6.2@P Channel
Maximum Power Dissipation on PCB @ TC=25°C (W)	2
Maximum Pulsed Drain Current @ TC=25°C (A)	40
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)	110
Typical Diode Forward Voltage (V)	0.8
Typical Gate Plateau Voltage (V)	2.5@N Channel
Typical Reverse Recovery Time (ns)	50@N Channel
Maximum Diode Forward Voltage (V)	1.2
Original Package	SOIC N
Pin Count	8
Standard Package Method	SOP
Terminal Form	Surface Mount
Package Height	1.55(Max)
Package Length	5(Max)
Package Width	4(Max)
PCB changed	8

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Products specifications

EU RoHS	Compliant
ECCN (US)	EAR99
Part Status	Obsolete
HTS	8541.29.00.95
Automotive	No
PPAP	No
Product Category	Power MOSFET
Configuration	Dual Dual Drain
Process Technology	TrenchFET
Channel Mode	Enhancement
Channel Type	N
Number of Elements per pcs	2
Maximum Drain Source Voltage (V)	20
Maximum Gate Source Voltage (V)	±16@N Channel
Maximum Gate Threshold Voltage (V)	1.8@N Channel
Operating Junction Temperature (°C)	-55 to 150
Maximum Continuous Drain Current (A)	7.2@N Channel
Maximum Gate Source Leakage Current (nA)	100
Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	14.5@10V@N Channel
Typical Gate Charge @ Vgs (nC)	11.5@4.5V@N Channel
Typical Gate to Drain Charge (nC)	3.3@N Channel
Typical Gate to Source Charge (nC)	4.1@P Channel
Minimum Gate Threshold Voltage (V)	0.6
Typical Output Capacitance (pF)	399@N Channel
Maximum Power Dissipation (mW)	2000
Typical Fall Time (ns)	15@N Channel
Typical Rise Time (ns)	12@N Channel
Typical Turn-Off Delay Time (ns)	55@N Channel
Typical Turn-On Delay Time (ns)	25@P Channel
Operating Temperature-Min	-55
Operating Temperature-Max	150
Packing Method	Tape and Reel
Maximum Positive Gate Source Voltage (V)	12
Maximum Continuous Drain Current on PCB @ TC=25°C (A)	6.2@P Channel
Maximum Power Dissipation on PCB @ TC=25°C (W)	2
Maximum Pulsed Drain Current @ TC=25°C (A)	40
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)	110
Typical Diode Forward Voltage (V)	0.8
Typical Gate Plateau Voltage (V)	2.5@N Channel
Typical Reverse Recovery Time (ns)	50@N Channel
Maximum Diode Forward Voltage (V)	1.2
Original Package	SOIC N
Pin Count	8
Standard Package Method	SOP
Terminal Form	Surface Mount
Package Height	1.55(Max)
Package Length	5(Max)
Package Width	4(Max)
PCB changed	8