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    CD4027BE

    SKU: 81865
    Manufacturer: Texas Instruments
    Flip Flop JK-Master-Slave Type Pos-Edge 2-Element 16-Pin PDIP Tube
    34840 parts IN STOCK
    Shipped from :
    Netherlands
    Expected Ships :
    Rohs State : Need to verify

    QUANTITY

    Increments of 0 pcs
    Products specifications
    EU RoHS Compliant
    ECCN (US) EAR99
    Part Status Active
    HTS 8542.39.00.01
    Automotive No
    PPAP No
    Logic Family CD4000
    Logic Function JK-Master-Slave Type
    Number of Channels per Chip 2
    Number of Elements per pcs 2
    Number of Element Inputs 2
    Number of Element Outputs 1
    Bus Hold No
    Set/Reset Set/Reset
    Polarity Inverting/Non-Inverting
    Triggering Type Positive-Edge
    Maximum Propagation Delay Time @ Maximum CL (ns) 300@5V
    Absolute Propagation Delay Time (ns) 400
    Process Technology CMOS
    Input Signal Type Single-Ended
    Maximum Low Level Output Current (mA) 4.2(Min)
    Maximum High Level Output Current (mA) -4.2(Min)
    Operating Supply Voltage-Min (V) 3
    Typical Operating Supply Voltage (V) 3.3
    Operating Supply Voltage-Max (V) 18
    Maximum Quiescent Current (mA) 0.02
    Propagation Delay Test Condition (pF) 50
    Operating Temperature-Min -55
    Operating Temperature-Max 125
    Supplier Temperature Grade Military
    Packing Method Tube
    Standard Package Method DIP
    Original Package PDIP
    Pin Count 16
    Terminal Form Through Hole
    Package Height 5.08(Max) - 0.51(Min)
    Package Length 19.69(Max)
    Package Width 6.6(Max)
    PCB changed 16
    Products specifications
    EU RoHS Compliant
    ECCN (US) EAR99
    Part Status Active
    HTS 8542.39.00.01
    Automotive No
    PPAP No
    Logic Family CD4000
    Logic Function JK-Master-Slave Type
    Number of Channels per Chip 2
    Number of Elements per pcs 2
    Number of Element Inputs 2
    Number of Element Outputs 1
    Bus Hold No
    Set/Reset Set/Reset
    Polarity Inverting/Non-Inverting
    Triggering Type Positive-Edge
    Maximum Propagation Delay Time @ Maximum CL (ns) 300@5V
    Absolute Propagation Delay Time (ns) 400
    Process Technology CMOS
    Input Signal Type Single-Ended
    Maximum Low Level Output Current (mA) 4.2(Min)
    Maximum High Level Output Current (mA) -4.2(Min)
    Operating Supply Voltage-Min (V) 3
    Typical Operating Supply Voltage (V) 3.3
    Operating Supply Voltage-Max (V) 18
    Maximum Quiescent Current (mA) 0.02
    Propagation Delay Test Condition (pF) 50
    Operating Temperature-Min -55
    Operating Temperature-Max 125
    Supplier Temperature Grade Military
    Packing Method Tube
    Standard Package Method DIP
    Original Package PDIP
    Pin Count 16
    Terminal Form Through Hole
    Package Height 5.08(Max) - 0.51(Min)
    Package Length 19.69(Max)
    Package Width 6.6(Max)
    PCB changed 16