FDS6982

SKU: 11712

Manufacturer: onsemi

Trans MOSFET N-CH 30V 6.3A/8.6A 8-Pin SOIC N T/R

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Netherlands

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Products specifications

EU RoHS	Compliant
ECCN (US)	EAR99
Part Status	Obsolete
HTS	8541.21.00.95
Automotive	No
PPAP	No
Product Category	Power MOSFET
Configuration	Dual Dual Drain
Process Technology	PowerTrench
Channel Mode	Enhancement
Channel Type	N
Number of Elements per pcs	2
Maximum Drain Source Voltage (V)	30
Maximum Gate Source Voltage (V)	±20
Maximum Gate Threshold Voltage (V)	3
Operating Junction Temperature (°C)	-55 to 150
Maximum Continuous Drain Current (A)	8.6@Q 2
Maximum Gate Source Leakage Current (nA)	100
Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	28@10V@Q 1
Typical Gate Charge @ Vgs (nC)	8.5@5V@Q 1
Typical Gate to Drain Charge (nC)	3.1@Q 1
Typical Gate to Source Charge (nC)	2.4@Q 1
Typical Input Capacitance @ Vds (pF)	760@10V@Q 1
Typical Reverse Transfer Capacitance @ Vds (pF)	160@10V@Q 2
Minimum Gate Threshold Voltage (V)	1
Typical Output Capacitance (pF)	160@Q 1
Maximum Power Dissipation (mW)	2000
Typical Fall Time (ns)	7@Q 1
Typical Rise Time (ns)	14@Q 1
Typical Turn-Off Delay Time (ns)	21@Q 1
Typical Turn-On Delay Time (ns)	10@Q 1
Operating Temperature-Min	-55
Operating Temperature-Max	150
Packing Method	Tape and Reel
Maximum Power Dissipation on PCB @ TC=25°C (W)	1.6
Maximum Pulsed Drain Current @ TC=25°C (A)	20@Q 1
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)	135
Typical Diode Forward Voltage (V)	0.74@Q 1
Typical Gate Plateau Voltage (V)	2.8@Q 1
Maximum Diode Forward Voltage (V)	1.2
Typical Gate Threshold Voltage (V)	1.6@Q 1
Maximum Positive Gate Source Voltage (V)	20
Maximum Continuous Drain Current on PCB @ TC=25°C (A)	8.6@Q 2
Original Package	SOIC N
Pin Count	8
Standard Package Method	SOP
Terminal Form	Surface Mount
Package Height	1.5(Max)
Package Length	4.9
Package Width	3.9
PCB changed	8

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Products specifications

EU RoHS	Compliant
ECCN (US)	EAR99
Part Status	Obsolete
HTS	8541.21.00.95
Automotive	No
PPAP	No
Product Category	Power MOSFET
Configuration	Dual Dual Drain
Process Technology	PowerTrench
Channel Mode	Enhancement
Channel Type	N
Number of Elements per pcs	2
Maximum Drain Source Voltage (V)	30
Maximum Gate Source Voltage (V)	±20
Maximum Gate Threshold Voltage (V)	3
Operating Junction Temperature (°C)	-55 to 150
Maximum Continuous Drain Current (A)	8.6@Q 2
Maximum Gate Source Leakage Current (nA)	100
Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	28@10V@Q 1
Typical Gate Charge @ Vgs (nC)	8.5@5V@Q 1
Typical Gate to Drain Charge (nC)	3.1@Q 1
Typical Gate to Source Charge (nC)	2.4@Q 1
Typical Input Capacitance @ Vds (pF)	760@10V@Q 1
Typical Reverse Transfer Capacitance @ Vds (pF)	160@10V@Q 2
Minimum Gate Threshold Voltage (V)	1
Typical Output Capacitance (pF)	160@Q 1
Maximum Power Dissipation (mW)	2000
Typical Fall Time (ns)	7@Q 1
Typical Rise Time (ns)	14@Q 1
Typical Turn-Off Delay Time (ns)	21@Q 1
Typical Turn-On Delay Time (ns)	10@Q 1
Operating Temperature-Min	-55
Operating Temperature-Max	150
Packing Method	Tape and Reel
Maximum Power Dissipation on PCB @ TC=25°C (W)	1.6
Maximum Pulsed Drain Current @ TC=25°C (A)	20@Q 1
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)	135
Typical Diode Forward Voltage (V)	0.74@Q 1
Typical Gate Plateau Voltage (V)	2.8@Q 1
Maximum Diode Forward Voltage (V)	1.2
Typical Gate Threshold Voltage (V)	1.6@Q 1
Maximum Positive Gate Source Voltage (V)	20
Maximum Continuous Drain Current on PCB @ TC=25°C (A)	8.6@Q 2
Original Package	SOIC N
Pin Count	8
Standard Package Method	SOP
Terminal Form	Surface Mount
Package Height	1.5(Max)
Package Length	4.9
Package Width	3.9
PCB changed	8