5SGSMD8K3F40C2N

SKU: 130523

Manufacturer: Intel

FPGA Stratix® V GS Family 695000 Cells 28nm Technology 0.85V 1517-Pin FC-FBGA Tray

1180 parts IN STOCK

Shipped from :

Netherlands

Expected Ships :

Rohs State : Need to verify

Increments of 0 pcs

Products specifications

EU RoHS	Compliant with Exemption
ECCN (US)	3A001.a.7.a
Part Status	Obsolete
HTS	8542.39.00.01
Automotive	No
PPAP	No
Family Name	Stratix® V GS
Process Technology	28nm
User I/Os	696
Number of Registers	1050000
Shift Registers	Utilize Memory
Operating Supply Voltage (V)	0.85
Logic Elements	695000
Number of Multipliers	3926 (18x18)
Program Memory Type	SRAM
Embedded Memory (Kbit)	51200
Total Number of Block RAM	2567
EMACs	2
IP Core	RapidIO to AXI Bridge Controller (RAB)
Provider Name	Altera/Barco Silex/Mobiveil, Inc
Device Logic Units	695000
Number of Global Clocks	16
Device Number of DLLs/PLLs	28
Transceiver Channels	48
Transceiver Speed (Gbps)	14.1
JTAG Support	Yes
Dedicated DSP	1963
PCIe	4
Programmability	Yes
Reprogrammability Support	Yes
Number of Look-up Table Input	8
Copy Protection	No
In-System Programmability	Yes
Speed Grade	2
Differential I/O Standards	LVDS
Single-Ended I/O Standards	LVTTL
External Memory Interface	QDRII+SRAM
Operating Supply Voltage-Min (V)	0.82
Operating Supply Voltage-Max (V)	0.88
I/O Voltage (V)	1.2
Operating Temperature-Min	0
Operating Temperature-Max	85
Supplier Temperature Grade	Commercial
Packing Method	Tray
Tradename	Stratix
Original Package	FC-FBGA
Pin Count	1517
Standard Package Method	BGA
Terminal Form	Surface Mount
Package Height	3.2
Package Length	40
Package Width	40
PCB changed	1517

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Products specifications

EU RoHS	Compliant with Exemption
ECCN (US)	3A001.a.7.a
Part Status	Obsolete
HTS	8542.39.00.01
Automotive	No
PPAP	No
Family Name	Stratix® V GS
Process Technology	28nm
User I/Os	696
Number of Registers	1050000
Shift Registers	Utilize Memory
Operating Supply Voltage (V)	0.85
Logic Elements	695000
Number of Multipliers	3926 (18x18)
Program Memory Type	SRAM
Embedded Memory (Kbit)	51200
Total Number of Block RAM	2567
EMACs	2
IP Core	RapidIO to AXI Bridge Controller (RAB)
Provider Name	Altera/Barco Silex/Mobiveil, Inc
Device Logic Units	695000
Number of Global Clocks	16
Device Number of DLLs/PLLs	28
Transceiver Channels	48
Transceiver Speed (Gbps)	14.1
JTAG Support	Yes
Dedicated DSP	1963
PCIe	4
Programmability	Yes
Reprogrammability Support	Yes
Number of Look-up Table Input	8
Copy Protection	No
In-System Programmability	Yes
Speed Grade	2
Differential I/O Standards	LVDS
Single-Ended I/O Standards	LVTTL
External Memory Interface	QDRII+SRAM
Operating Supply Voltage-Min (V)	0.82
Operating Supply Voltage-Max (V)	0.88
I/O Voltage (V)	1.2
Operating Temperature-Min	0
Operating Temperature-Max	85
Supplier Temperature Grade	Commercial
Packing Method	Tray
Tradename	Stratix
Original Package	FC-FBGA
Pin Count	1517
Standard Package Method	BGA
Terminal Form	Surface Mount
Package Height	3.2
Package Length	40
Package Width	40
PCB changed	1517